1. Field of the Invention
The present invention relates to a semiconductor device.
2. Background Art
Semiconductor devices in which semiconductor elements are mounted on a metal substrate have been known, as disclosed, e.g., in Japanese Laid-Open Patent Publication No. H05-67727. In the semiconductor device disclosed in this publication, copper circuits are bonded or soldered to the insulating layer formed on the entire surface of a metal substrate. Specifically, in the manufacture of the semiconductor device, solder cream is printed onto portions of a copper circuit laminated to the metal substrate, power semiconductor chips are then mounted on the copper circuit pattern, and these and other components are soldered together in a reflow oven. The circuits on the metal substrate are then interconnected by wire bonding, and the substrate (with the interconnected circuits thereon) is mounted in a case, thereby completing the manufacture of the semiconductor device.
Other prior art includes Japanese Laid-Open Patent Publication No. H5-67727, Japanese Laid-Open Patent Publication No. H5-37105, Japanese Laid-Open Patent Publication No. 2007-184315, Japanese Laid-Open Patent Publication No. H9-232512, Japanese Laid-Open Patent Publication No. 2000-216332, Japanese Laid-Open Patent Publication No. 2002-76197, Japanese Laid-Open Patent Publication No. 2001-36004, and Japanese Laid-Open Patent Publication No. 2007-157863.
Thus, the above prior art semiconductor device includes a metal substrate on which semiconductor elements and other components are mounted. This metal substrate comprises a metal plate of copper, etc. with an insulating layer thereon which is formed, e.g., by bonding an insulating sheet to the surface of the metal plate. A circuit pattern of a conductive material such as copper is formed on the insulating layer. It has been found, however, that the difference in coefficient of liner expansion between the insulating layer and the conductive material circuit pattern thereon may cause cracking in the metal substrate, resulting in delamination of the circuit pattern from the insulating layer.